The USB 2.0 standard effectively requires a clock recovery within 12 clock periods. The shortness of this time period is a challenge for CDR designers.
Typically, analog CDRs require more than 12 clock periods to recover a clock. An open loop CDR using two Voltage Control Oscillators (VCOs) can recover a clock within 12 clock periods; however, the power consumed by the VCOs can be significant.